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| QUINT AND/NAND GATE FEATURES s Max. propagation delay of 1050ps s IEE min. of -60mA s Extended supply voltage option: VEE = -4.2V to -5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75K input pull-down resistors s 40% faster than Fairchild 300K at lower power s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages SY100S304 DESCRIPTION The SY100S304 is an ultra-fast quint AND/NAND gate designed for use in high-performance ECL systems. This device also features a Function (F) output which is the wireNOR of the AND gate outputs. The inputs on the device have 75K pull-down resistors. PIN CONFIGURATIONS D1a Oa VEES D2a Oa Ob Ob 4 3 2 1 28 27 26 19 20 21 22 23 24 25 11 10 9 8 7 6 5 D1b D2b VEE VEES D1c D2c D2d 12 13 14 15 16 17 18 Oc Oc VCCA VCC VCC F Od Top View PLCC J28-1 BLOCK DIAGRAM F Oe Oe D1d D1e D2e VEES Od D2d D2c D1c VEE D2b D1a D2a D1b D2b D1c D2c D1d D2d D1e D2e Oa Oa Ob Ob Oc Oc Od Od Oe Oe D1d D1e D2e Oe Oe Od 1 2 3 4 5 6 24 23 22 21 20 19 18 Top View Flatpack F24-1 17 16 15 14 D1b D2a D1a Oa Oa Ob Ob 13 7 8 9 10 11 12 F VCC VCCA Od Oc Oc PIN NAMES Pin Dna - Dne E Oa - Oe Oa - Oe VEES VCCA Function Data Inputs (n-1...5) Enable Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs Rev.: G Amendment: /0 1 Issue Date: July, 1999 Micrel SY100S304 DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND Symbol IIH Parameter Input HIGH Current D2a -- D2e D1a -- D1e Power Supply Current Min. -- -- -60 Typ. -- -- -40 Max. 250 250 -30 mA Inputs Open Unit A Condition VIN = VIH (Max.) IEE AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tTLH tTHL Parameter Propagation Delay Dna -- Dne to O, O Propagation Delay Data to F Transition Time 20% to 80%, 80% to 20% Min. 300 600 300 Max. 1150 1650 900 TA = +25C Min. 300 600 300 Max. 1150 1650 900 TA = +85C Min. 300 600 300 Max. 1150 1650 900 Unit ps ps ps Condition PLCC VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tTLH tTHL Parameter Propagation Delay Dna -- Dne to O, O Propagation Delay Data to F Transition Time 20% to 80%, 80% to 20% Min. 300 600 300 Max. 1050 1550 900 TA = +25C Min. 300 600 300 Max. 1050 1550 900 TA = +85C Min. 300 600 300 Max. 1050 1550 900 Unit ps ps ps Condition 2 Micrel SY100S304 TIMING DIAGRAM 0.7 0.1 ns INPUT 80% 50% 20% -1.69V TRUE tPHL tPLH 0.7 0.1 ns -0.95V 50% OUTPUT tPLH tPHL 80% 50% 20% tTLH tTHL COMPLEMENT Propagation Delay and Transition Times NOTE: VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND PRODUCT ORDERING CODE Ordering Code SY100S304FC SY100S304JC SY100S304JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial 3 Micrel SY100S304 24 LEAD CERPACK (F24-1) Rev. 03 4 Micrel SY100S304 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 5 |
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